`include "defines.v"
module hilo_reg(
	input wire clk,
	input wire rst,
	input wire write_ce,
	input wire[31:0] hi_i,
	input wire[31:0] lo_i,
	output reg[31:0] hi_o,
	output reg[31:0] lo_o
);
	always@(posedge clk)
		if(rst == `RstEnable)
		begin
			hi_o <= `ZeroWord;
			lo_o <= `ZeroWord;
		end
		else if(write_ce == `WriteEnable)
		begin
			hi_o <= hi_i;
			lo_o <= lo_i;
		end


endmodule